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february 2012 ? 2012 fairchild semiconductor corporation www.fairchildsemi.com fan3121 / fan3122_f085 ? rev. 1.0.0 fan3121 / fan3122_f085 ? single 9a high-speed, low-side gate driver fan3121 / fan3122_f085 single 9a high-speed, low-side gate driver features ? qualified to aec q-100 ? 4.5 to 18v operating range ? 11.4a peak sink at v dd = 12v ? 9.7a sink / 7.1a source at v out = 6v ? inverting configuration (fan3121) and non-inverting configuration (fan3122) ? internal resistors turn driver off if no inputs ? 23ns/19ns typical rise/fall times with 10nf load ? 20ns typical propagation delay time ? choice of ttl or cmos input thresholds ? millerdrive? technology ? 8-lead soic package ? rated from ?40c to +125c applications ? synchronous rectifier circuits ? high-efficiency mosfet switching ? switch-mode power supplies ? dc-to-dc converters ? motor control description the fan3121 and fan3122 mosfet drivers are designed to drive n-channel enhancement mosfets in low-side switching applications by providing high peak current pulses. the drivers ar e available with either ttl (fan312xt) or cmos (fan312xc) input thresholds. internal circuitry provides an under-voltage lockout function by holding the output low until the supply voltage is within the operating range. fan312x drivers incorporate the millerdrive? architecture for the final output stage. this bipolar / mosfet combination provides the highest peak current during the miller plateau stage of the mosfet turn-on / turn-off process. the fan3121 and fan3122 drivers implement an enable function on pin 3 (en), previously unused in the industry-standard pin-out. the pin is internally pulled up to v dd for active high logic and can be left open for standard operation. 1 2 3 6 7 8 4 5 vdd gnd en in vdd out gnd out 1 2 3 6 7 8 4 5 en in vdd gnd vdd gnd out out figure 1. fan3121 pin configuration figure 2. fan3122 pin configuration
? 2012 fairchild semiconductor corporation www.fairchildsemi.com fan3121 / fan3122_f085 ? rev. 1.0.0 2 fan3121 / fan3122_f085 ? single 9a high-speed, low-side gate driver ordering information part number logic input threshold package eco status packing method quantit y per reel fan3121cmx_f085 inverting channels + enable cmos soic-8 rohs tape & reel 2,500 fan3121tmx_f085 ttl soic-8 rohs tape & reel 2,500 fan3122cmx_f085 non-inverting channels + enable cmos soic-8 rohs tape & reel 2,500 fan3122tmx_f085 ttl soic-8 rohs tape & reel 2,500 for fairchild?s definition of ?green? eco status, please visit: http://www.fairchildsemi.com/company/green/rohs_green.html . package outline figure 3. soic-8 (top view) thermal characteristics (1) package ? jl (2) ? jt (3) ? ja (4) ? jb (5) ? jt (6) units 8-pin small outline integrated circuit (soic) 38 29 87 41 2.3 c/w notes: 1. estimates derived from thermal simulation ; actual values depend on the application. 2. theta_jl ( ? jl ): thermal resistance between the semiconductor ju nction and the bottom surface of all the leads (including any thermal pad) that are typically soldered to a pcb. 3. theta_jt ( ? jt ): thermal resistance between the semiconductor junction and the top surface of the package, assuming it is held at a uniform temperature by a top-side heatsink. 4. theta_ja ( ja ): thermal resistance between junction and ambien t, dependent on the pcb design, heat sinking, and airflow. the value given is for natural convection with no heatsink, as specified in jedec standards jesd51-2, jesd51-5, and j esd51-7, as appropriate. 5. psi_jb ( ? jb ): thermal characterization parameter providin g correlation between semiconductor junction temperature and an application circuit board reference poin t for the thermal environment defined in note 4. for the soic-8 package, the board reference is de fined as the pcb copper adjacent to pin 6. 6. psi_jt ( ? jt ): thermal characterization par ameter providing correlation be tween the semiconductor junction temperature and the center of the top of the package for the thermal environment defined in note 4.
? 2012 fairchild semiconductor corporation www.fairchildsemi.com fan3121 / fan3122_f085 ? rev. 1.0.0 3 fan3121 / fan3122_f085 ? single 9a high-speed, low-side gate driver 1 2 3 6 7 8 4 5 vdd gnd en in vdd out gnd out 1 2 3 6 7 8 4 5 en in vdd gnd vdd gnd out out figure 4. fan3121 pin assignments (repeated) figure 5. fan3122 pin assignments (repeated) pin definitions fan3121 fan3122 name description 3 3 en enable input . pull pin low to inhibit driver. en has logic thresholds for both ttl and cmos in thresholds. 4, 5 4, 5 gnd ground . common ground reference for input and output circuits. 2 2 in input . 6, 7 out gate drive output . held low unless required input is present and v dd is above the uvlo threshold. 6, 7 out gate drive output (inverted from the input). held low unless required input is present and v dd is above the uvlo threshold. 1, 8 1, 8 v dd supply voltage . provides power to the ic. output logic fan3121 fan3122 en in out en in out 0 0 0 0 0 (7) 0 0 1 (7) 0 0 1 0 1 (7) 0 1 1 (7) 0 (7) 0 1 (7) 1 (7) 0 1 (7) 1 1 note: 7. default input signal if no external connection is made.
? 2012 fairchild semiconductor corporation www.fairchildsemi.com fan3121 / fan3122_f085 ? rev. 1.0.0 4 fan3121 / fan3122_f085 ? single 9a high-speed, low-side gate driver block diagram en 3 8 v dd 6 5 gnd uvlo v dd_ok in 2 100k 100k 100k v dd inverting (fan3121) non-inverting (fan3122) 7 v dd 1 4 gnd out (fan3122) out (fan3121) out (fan3122) out (fan3121) 100k figure 6. block diagram
? 2012 fairchild semiconductor corporation www.fairchildsemi.com fan3121 / fan3122_f085 ? rev. 1.0.0 5 fan3121 / fan3122_f085 ? single 9a high-speed, low-side gate driver absolute maximum ratings stresses exceeding the absolute maximum ratings may damage the device. the device may not function or be operable above the recommended operating conditions and st ressing the parts to these levels is not recommended. in addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. the absolute maximum ratings are stress ratings only. symbol parameter min. max. unit v dd v dd to gnd -0.3 20.0 v v en en to gnd gnd - 0.3 v dd + 0.3 v v in in to gnd gnd - 0.3 v dd + 0.3 v v out out to gnd gnd - 0.3 v dd + 0.3 v t l lead soldering temperature (10 seconds) +260 oc t j junction temperature -55 +150 oc t stg storage temperature -65 +150 oc esd human body model, jedec jesd22-a114 2 kv recommended operating conditions the recommended operating conditions table defines the conditions for actual device operation. recommended operating conditions are specified to ens ure optimal performance to the datasheet specifications. fairchild does not recommend exceeding them or designi ng to absolute maximum ratings. symbol parameter min. max. unit v dd supply voltage range 4.5 18.0 v v en enable voltage en 0 v dd v v in input voltage in 0 v dd v t a operating ambient temperature -40 +125 oc
? 2012 fairchild semiconductor corporation www.fairchildsemi.com fan3121 / fan3122_f085 ? rev. 1.0.0 6 fan3121 / fan3122_f085 ? single 9a high-speed, low-side gate driver electrical characteristics unless otherwise noted, v dd =12v and t j =-40c to +125c. currents are defined as positive into the device and negative out of the device. symbol parameter conditions min. typ. max. unit supply v dd operating range 4.5 18.0 v i dd supply current, inputs / en not connected ttl 0.65 0.90 ma cmos (8) 0.58 0.85 v on turn-on voltage 3.5 4.0 4.3 v v off turn-off voltage 3.25 3.75 4.15 v inputs (fan312xt) (9) v il_t inx logic low threshold 0.8 1.0 v v ih_t inx logic high threshold 1.7 2.0 v i inx_t non-inverting input current in = 0v -1.5 1.5 a i inx_t non-inverting input current in = v dd 90 120 175.0 a i inx_t inverting input current in = 0v -175.0 -120 -90 a i inx_t inverting input current in = v dd -1.5 1.5 a v hys_t ttl logic hysteresis voltage 0.40 0.70 0.85 v inputs (fan312xc) (9) v il_c inx logic low threshold 30 38 %v dd v ih_c inx logic high threshold 55 70 %v dd i inx_c non-inverting input current in = 0v -1.5 1.5 a i inx_c non-inverting input current in = v dd 90 120 175 a i inx_c inverting input current in = 0v -175 -120 -90 a i inx_c inverting input current in = v dd -1.5 1.5 a v hys_c cmos logic hysteresis voltage 12 17 24 %v dd enable (fan3121, fan3122) v enl enable logic low threshold en from 5v to 0v 1.2 1.6 2.0 v v enh enable logic high threshold en from 0v to 5v 1.8 2.2 2.6 v v hys_t ttl logic hysteresis voltage 0.2 0.6 0.8 v r pu enable pull-up resistance 68 100 134 k ? t d1 , t d2 propagation delay, en rising (10) 8 17 27 ns t d1 , t d2 propagation delay, en falling (10) 14 21 33 ns notes: 8. lower supply current due to inactive ttl circuitry. 9. en inputs have modified ttl thre sholds; refer to the enable section. 10. see timing diagrams of figure 7 and figure 8.
? 2012 fairchild semiconductor corporation www.fairchildsemi.com fan3121 / fan3122_f085 ? rev. 1.0.0 7 fan3121 / fan3122_f085 ? single 9a high-speed, low-side gate driver electrical characteristics (continued) unless otherwise noted, v dd =12v and t j =-40c to +125c. currents are defined as positive into the device and negative out of the device. output i sink out current, mid-voltage, sinking (11) out at v dd /2, c load =1.0f, f=1khz 9.7 a i source out current, mid-voltage, sourcing (11) out at v dd /2, c load =1.0f, f=1khz 7.1 a i pk_sink out current, peak, sinking (11) c load =1.0f, f=1khz 11.4 a i pk_source out current, peak, sourcing (11) c load =1.0f, f=1khz 10.6 a v oh high level output voltage v oh = v dd C v out , i out = C 1ma 15 35 mv v ol low level output voltage i out = 1ma 10 25 mv t rise output rise time (12) c load =10nf 18 23 29 ns t fall output fall time (12) c load =10nf 11 19 27 ns t d1, t d2 output propagation delay, cmos inputs (12) 0 ? 12v in , 1v/ns slew rate 9 18 28 ns t d1, t d2 output propagation delay, ttl inputs (12) 0 ? 5v in , 1v/ns slew rate 9 23 35 ns notes: 11. not tested in production. 12. see timing diagrams of figure 7 and figure 8. timing diagrams figure 7. non-inverting figure 8. inverting
? 2012 fairchild semiconductor corporation www.fairchildsemi.com fan3121 / fan3122_f085 ? rev. 1.0.0 8 fan3121 / fan3122_f085 ? single 9a high-speed, low-side gate driver typical performance characteristics typical characteristics are provided at 25c and v dd =12v unless otherwise noted. figure 9. i dd (static) vs. supply voltage (13) figure 10. i dd (static) vs. supply voltage (13) figure 11. i dd (no-load) vs. frequency figure 12. i dd (no-load) vs. frequency figure 13. i dd (10nf load) vs. frequency figure 14. i dd (10nf load) vs. frequency
? 2012 fairchild semiconductor corporation www.fairchildsemi.com fan3121 / fan3122_f085 ? rev. 1.0.0 9 fan3121 / fan3122_f085 ? single 9a high-speed, low-side gate driver typical performance characteristics typical characteristics are provided at 25c and v dd =12v unless otherwise noted. figure 15. i dd (static) vs. temperature (13) figure 16. i dd (static) vs. temperature (13) figure 17. input thresholds vs. supply voltage figure 18. input thresholds vs. supply voltage figure 19. input thresholds % vs. supply voltage figure 20. enable thresh olds vs. supply voltage
? 2012 fairchild semiconductor corporation www.fairchildsemi.com fan3121 / fan3122_f085 ? rev. 1.0.0 10 fan3121 / fan3122_f085 ? single 9a high-speed, low-side gate driver typical performance characteristics typical characteristics are provided at 25c and v dd =12v unless otherwise noted. figure 21. cmos input thresholds vs. temperature figure 22. ttl input thresholds vs. temperature figure 23. enable thresholds vs. temperature figure 24. uvlo thresholds vs. temperature figure 25. uvlo hysteresis vs. temperature figure 26. propagation delay vs. supply voltage
? 2012 fairchild semiconductor corporation www.fairchildsemi.com fan3121 / fan3122_f085 ? rev. 1.0.0 11 fan3121 / fan3122_f085 ? single 9a high-speed, low-side gate driver typical performance characteristics typical characteristics are provided at 25c and v dd =12v unless otherwise noted. figure 27. propagation delay vs. supply voltage figure 28. propagation delay vs. supply voltage figure 29. propagation delay vs. supply voltage figure 30. propagation delay vs. supply voltage figure 31. propagation delays vs. temperature figure 32. propagation delays vs. temperature
? 2012 fairchild semiconductor corporation www.fairchildsemi.com fan3121 / fan3122_f085 ? rev. 1.0.0 12 fan3121 / fan3122_f085 ? single 9a high-speed, low-side gate driver typical performance characteristics typical characteristics are provided at 25c and v dd =12v unless otherwise noted. figure 33. propagation delays vs. temperature figure 34. propagation delays vs. temperature figure 35. propagation delays vs. temperature figure 36. fall time vs. supply voltage figure 37. rise time vs. supply voltage figure 38. rise and fall time vs. temperature
? 2012 fairchild semiconductor corporation www.fairchildsemi.com fan3121 / fan3122_f085 ? rev. 1.0.0 13 fan3121 / fan3122_f085 ? single 9a high-speed, low-side gate driver typical performance characteristics typical characteristics are provided at 25c and v dd =12v unless otherwise noted. figure 39. rise / fall waveforms with 10nf load figure 40. quasi-static source current with v dd =12v (14) figure 41. quasi-static sink current with v dd =12v (14) figure 42. quasi-static source current with v dd =8v (14) 470f al. el. v dd v out 1f ceramic (2) x 4.7f ceramic c load 1f i out in 1khz current probe lecroy ap015 fan3121/22 figure 43. quasi-static sink current with v dd =8v (14) figure 44. quasi-static i out / v out test circuit notes: 13. for any inverting inputs pulled low, non-inverting inputs pulled high, or outputs driven high; static i dd increases by the current flowing through the corres ponding pull-up/down resi stor, shown in figure 6. 14. the initial spike in each current waveform is a m easurement artifact caused by the stray inductance of the current-measurement loop.
? 2012 fairchild semiconductor corporation www.fairchildsemi.com fan3121 / fan3122_f085 ? rev. 1.0.0 14 fan3121 / fan3122_f085 ? single 9a high-speed, low-side gate driver applications information the fan3121 and fan3122 family offers versions in either ttl or cmos input configuration. in the fan3121t and fan3122t, the input thresholds meet industry-standard ttl-logic thresholds independent of the v dd voltage, and there is a hysteresis voltage of approximately 0.7v. these levels permit the inputs to be driven from a range of input logic signal levels for which a voltage over 2v is considered logic high. the driving signal for the ttl inputs should have fast rising and falling edges with a slew rate of 6v/s or faster, so the rise time from 0 to 3.3v should be 550ns or less. the fan3121 and fan3122 output can be enabled or disabled using the en pin with a very rapid response time. if en is not externally connected, an internal pull- up resistor enables the driv er by default. the en pin has logic thresholds for parts wi th either ttl or cmos in thresholds. in the fan3121c and fan3122c, the logic input thresholds are dependent on the v dd level and, with v dd of 12v, the logic rising edge threshold is approximately 55% of v dd and the input falling edge threshold is approximately 38% of v dd . the cmos input configuration offers a hysteresis voltage of approximately 17% of v dd . the cmos inputs can be used with relatively slow edges (approaching dc) if good decoupling and bypass techniques are incorporated in the system design to prevent noise from violating the input voltage hysteresis window. this allows setting precise timing intervals by fitting an r-c circuit between the controlling signal and the in pin of the driver. the slow rising edge at the in pin of the driver introduces a delay between the controlling signal and the out pin of the driver. static supply current in the i dd (static) typical perfor mance characteristics, the curves are produced with all inputs / enables floating (out is low) and indicates the lowest static i dd current for the tested configuration. for other states, additional current flows through the 100k ? resistors on the inputs and outputs, as shown in the block diagram (see figure 6) . in these cases, the actual static i dd current is the value obtained from the curves, plus this additional current. millerdrive? gate-drive technology fan312x gate drivers incorporate the millerdrive? architecture shown in figure 45. for the output stage, a combination of bipolar and mos devices provide large currents over a wide range of supply voltage and temperature variations. the bipolar devices carry the bulk of the current as out swings between 1/3 to 2/3 v dd and the mos devices pull the output to the high or low rail. the purpose of the miller drive? architecture is to speed up switching by providing high current during the miller plateau region when the gate-drain capacitance of the mosfet is being charged or discharged as part of the turn-on / turn-off process. for applications with zero voltage switching during the mosfet turn-on or turn-off interval, the driver supplies high peak current for fast switching, even though the miller plateau is not present. this situation often occurs in synchronous rectifier applications because the body diode is generally conducting before the mosfet is switched on. the output pin slew rate is determined by v dd voltage and the load on the output. it is not user adjustable, but a series resistor can be added if a slower rise or fall time at the mosfet gate is needed. figure 45. miller drive? output architecture under-voltage lockout (uvlo) the fan312x startup logic is optimized to drive ground- referenced n-channel mosfets with an under-voltage lockout (uvlo) function to ensure that the ic starts in an orderly fashion. when v dd is rising, yet below the 4.0v operational level, this circuit holds the output low, regardless of the status of the input pins. after the part is active, the supply voltage must drop 0.25v before the part shuts down. this hysteresis helps prevent chatter when low v dd supply voltages have noise from the power switching. this configuration is not suitable for driving high-side p-channel mosfets because the low output voltage of the driver would turn the p-channel mosfet on with v dd below 4.0v. v dd bypassing and layout considerations the fan3121 and fan3122 are available in either 8-lead soic or mlp packages. in either package, the v dd pins 1 and 8 and the gnd pins 4 and 5 should be connected together on the pcb. in typical fan312x gate-drive r applications, high-current pulses are needed to charge and discharge the gate of a power mosfet in time intervals of 50ns or less. a bypass capacitor with low esr and esl should be connected directly between the v dd and gnd pins to provide these large current pulses without causing unacceptable ripple on the v dd supply. to meet these requirements in a small size, a ceramic capacitor of 1f
? 2012 fairchild semiconductor corporation www.fairchildsemi.com fan3121 / fan3122_f085 ? rev. 1.0.0 15 fan3121 / fan3122_f085 ? single 9a high-speed, low-side gate driver or larger is typically used, wi th a dielectric material such as x7r, to limit the change in capacitance over the temperature and / or voltage application ranges. figure 46 shows the pulsed gate drive current path when the gate driver is supplying gate charge to turn the mosfet on. the current is supplied from the local bypass capacitor c byp and flows through the driver to the mosfet gate and to ground. to reach the high peak currents possible with the fan312x family, the resistance and inductance in the path should be minimized. the localized c byp acts to contain the high peak current pulses within this driver-mosfet circuit, preventing them from distur bing the sensitive analog circuitry in the pwm controller. pwm v ds v dd c byp fan3121/2 figure 46. current path for mosfet turn-on figure 477 shows the path the current takes when the gate driver turns the mosfet off. ideally, the driver shunts the current directly to the source of the mosfet in a small circuit loop. for fast turn-off times, the resistance and inductance in this path should be minimized. pwm v ds v dd c byp fan3121/2 figure 47. current path for mosfet turn-off operational waveforms at power up, the fan3121 inverting driver shown in figure 48 holds the output low until the v dd voltage reaches the uvlo turn-on threshold, as indicated in figure 49. this facilitates proper startup control of low- side n-channel mosfets. v dd out in figure 48. inverting configuration the out pulses? magnitude follows v dd magnitude with the output polarity inverted from the input until steady- state v dd is reached. v dd in+ (v dd ) in- out turn-on threshold figure 49. inverting startup waveforms at power up, the fan3122 non-inverting driver, shown in figure 50, holds the output low until the v dd voltage reaches the uvlo turn-on threshold, as indicated in figure 511. the out pulses magnitude follow v dd magnitude until steady-state v dd is reached. v dd out in figure 50. non-inverting driver v dd in+ in- out turn-on threshold figure 51. non-inverting startup waveforms
? 2012 fairchild semiconductor corporation www.fairchildsemi.com fan3121 / fan3122_f085 ? rev. 1.0.0 16 fan3121 / fan3122_f085 ? single 9a high-speed, low-side gate driver thermal guidelines gate drivers used to switch mosfets and igbts at high frequencies can dissipat e significant amounts of power. it is important to determine the driver power dissipation and the resulting junction temperature in the application to ensure that the part is operating within acceptable temperature limits. the total power dissipation in a gate driver is the sum of two components, p gate and p dynamic : p total = p gate + p dynamic (1) gate driving loss: the most significant power loss results from supplying gate current (charge per unit time) to switch the load mosfet on and off at the switching frequency. the power dissipation that results from driving a mosfet at a specified gate- source voltage, v gs , with gate charge, q g , at switching frequency, f sw , is determined by: p gate = q g ? v gs ? f sw (2) dynamic pre-drive / shoot-through current: a power loss resulting from internal current consumption under dynamic operating conditions, including pin pull-up / pull-down resistors, can be obtained using the ?idd (no-load) vs. frequency? graphs in typical performance characteristics to determine the current i dynamic drawn from v dd under actual operating conditions: p dynamic = i dynamic ? v dd (3) once the power dissipated in the driver is determined, the driver junction rise with respect to circuit board can be evaluated using the fo llowing thermal equation, assuming ? jb was determined for a similar thermal design (heat sinking and air flow): t j = p total ? ? jb + t b (4) where: t j = driver junction temperature; ? jb = (psi) thermal characte rization parameter relating temperature rise to tota l power dissipation; and t b = board temperature in location as defined in the thermal characteristics table. in a full-bridge synchronous re ctifier application, shown in figure 522, each fan3122 drives a parallel combination of two high-current mosfets, (such as fdms8660s). the typical gate charge for each sr mosfet is 70nc with v gs = v dd = 9v. at a switching frequency of 300khz, the total power dissipation is: p gate = 2 ? 70nc ? 9v ? 300khz = 0.378w (5) p dynamic = 2ma ? 9v = 18mw (6) p total = 0.396w (7) the soic-8 has a junction-to-board thermal characterization parameter of ? jb = 42c/w. in a system application, the localized temperature around the device is a function of the layout and construction of the pcb along with airflow across the surfaces. to ensure reliable operation, the maximu m junction temperature of the device must be prevented from exceeding the maximum rating of 150c; with 80% derating, t j would be limited to 120c. rearranging equation 4 determines the board temperature required to maintain the junction temperature below 120c: t b,max = t j - p total ? ? jb (8) t b,max = 120c ? 0.396w ? 42c/w = 104c (9) .
? 2012 fairchild semiconductor corporation www.fairchildsemi.com fan3121 / fan3122_f085 ? rev. 1.0.0 17 fan3121 / fan3122_f085 ? single 9a high-speed, low-side gate driver typical application diagrams v in v out from a2 from a1 a1 a2 b1 b2 v dd in agnd out out v dd pgnd 1 2 3 6 7 8 4 5 sr en bias v dd in agnd out out v dd pgnd 1 2 3 6 7 8 4 5 en sr en en fan3122 fan3122 figure 52. full-bridge synchronous rectification v bias v in fan3121 pwm v out sr enable active high 1 2 3 45 6 7 8 v dd in en agnd v dd out out pgnd p1 (agnd) figure 53. hybrid synchronous rectification in a forward converter
? 2012 fairchild semiconductor corporation www.fairchildsemi.com fan3121 / fan3122_f085 ? rev. 1.0.0 18 fan3121 / fan3122_f085 ? single 9a high-speed, low-side gate driver table 1. related products part number type gate drive (15) (sink/src) input threshold logic package fan3100c single 2a +2.5a / -1.8a cmos single channel of two-input/one-output sot23-5 fan3100t single 2a +2.5a / -1.8a ttl single channel of two-input/one-output sot23-5 fan3226c dual 2a +2.4a / -1.6a cmos d ual inverting channels + dual enable soic8 fan3226t dual 2a +2.4a / -1.6a ttl dual inverting channels + dual enable soic8 fan3227c dual 2a +2.4a / -1.6a cmos dual non-inverting channels + dual enable soic8 fan3227t dual 2a +2.4a / -1.6a ttl dual non-inverting channels + dual enable soic8 fan3228c dual 2a +2.4a / -1.6a cmos dual channel s of two-input/one-output, pin config.1 soic8 fan3228t dual 2a +2.4a / -1.6a ttl dual channel s of two-input/one-output, pin config.1 soic8 fan3229c dual 2a +2.4a / -1.6a cmos dual channel s of two-input/one-output, pin config.2 soic8 fan3229t dual 2a +2.4a / -1.6a ttl dual channel s of two-input/one-output, pin config.2 soic8 fan3223c dual 4a +4.3a / -2.8a cmos d ual inverting channels + dual enable soic8 fan3223t dual 4a +4.3a / -2.8a ttl dual inverting channels + dual enable soic8 fan3224c dual 4a +4.3a / -2.8a cmos dual non-inverting channels + dual enable soic8 fan3224t dual 4a +4.3a / -2.8a ttl dual non-inverting channels + dual enable soic8 fan3225c dual 4a +4.3a / -2.8a cmos d ual channels of two-input/one-output soic8 fan3225t dual 4a +4.3a / -2.8a ttl dual channels of two-input/one-output soic8 fan3121c single 9a +9.7a / -7.1a cmos single inverting channels + enable soic8 fan3121t single 9a +9.7a / -7.1a ttl single inverting channels + enable soic8 fan3122c single 9a +9.7a / -7.1a cmos single non-inverting channels + enable soic8 fan3122t single 9a +9.7a / -7.1a ttl single non-inverting channels + enable soic8 note: 15. typical currents with out at 6v and v dd = 12v.
? 2012 fairchild semiconductor corporation www.fairchildsemi.com fan3121 / fan3122_f085 ? rev. 1.0.0 19 fan3121 / fan3122_f085 ? single 9a high-speed, low-side gate driver physical dimensions (continued) 8 [ 0 [ see detail a notes: unless otherwise specified a) this package conforms to jedec ms-012, variation aa, issue c, b) all dimensions are in millimeters. c) dimensions do not include mold flash or burrs. d) landpattern standard: soic127p600x175-8m. e) drawing filename: m08arev13 land pattern recommendation seating plane 0.10 c c gage plane x 45 detail a scale: 2:1 pin one indicator 4 8 1 c m ba 0.25 b 5 a 5.60 0.65 1.75 1.27 6.20 5.80 3.81 4.00 3.80 5.00 4.80 (0.33) 1.27 0.51 0.33 0.25 0.10 1.75 max 0.25 0.19 0.36 0.50 0.25 r0.10 r0.10 0.90 0.406 (1.04) option a - bevel edge option b - no bevel edge figure 54. 8-lead soic package drawings are provided as a service to customers consid ering fairchild components. drawings may change in any manner without notice. please note the revision and/or date on the drawing and contact a fairchild semiconductor representative to ver ify or obtain the most recent revision. package specifications do not expand the terms of fairchild?s worldwide terms and conditions, specifically the warranty therein, which covers fairchild products. always visit fairchild semiconductor?s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/ .
? 2012 fairchild semiconductor corporation www.fairchildsemi.com fan3121 / fan3122_f085 ? rev. 1.0.0 20 fan3121 / fan3122_f085 ? single 9a high-speed, low-side gate driver

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